There are current efforts in the telecommunications industry to provide broadband video services utilizing high performance technology at low cost. CMOS technology has the potential to provide broadband switching at low cost due to its high speed, high density, and low power dissipation.
The performance of broadband switches implemented in CMOS is affected by the specific configuration. In particular, a majority of conventional CMOS space switches encounter size and speed limitations due to stray capacitances in the array crosspoints. A relatively new switch architecture having a tree-switch configuration has been introduced recently that overcomes the aforecited limitations by isolating each crosspoint from the stray capacitances in the array. The configurations for implementing these tree-switches offer improvements in speed, chip area economy, and power dissipation. One such configuration is the 64.times.17 non-blocking crosspoint switch disclosed by Barber et al. at the 1988 IEEE International Solid-State Circuits Conference and is illustrated for exemplary purposes as an 8.times.1 tree-switch in FIG. 1.
As shown in FIG. 1, the tree-switch is constructed as a series of cascaded stages wherein the first stage consists of NAND gates each receiving an input signal and the remaining stages are comprised of switching nodes N2 having a NAND gate 20 cascaded to an inverter 21. A desirable feature of this switch is that each switching node drives only one other switching node in a following stage, thereby providing high speed. The control is relatively simple in that only the NAND gates in stage No. 1 receive control signals to effect a desired propagation path. For example, the combination of control signals as indicated in FIG. 1 are applied to stage No. 1 to sensitize the path through gates 10, 20, 30 and 40 so that only input signal 3 can propagate through the switch. Since only the gates in the sensitized path are operable to be switched due to the control signals, low power dissipation is possible.
Disadvantageously, an input signal propagating through the Barber et al. switch experiences an undesirable delay due to the cascaded sequence of NAND gate and associated inverter in each stage of the switch. Furthermore, the input signal is susceptible to pulse narrowing since rising and falling inputs could be treated differently by the cascaded sequence of NAND gate and inverter.
Regarding pulse-width narrowing, it is impossible for the rise and fall delay to stay exactly the same with variations in process, supply voltage, and environmental tolerances. Consequently, an unequal rise and fall delay causes the bit element pulse to shrink or expand thereby reducing operating speed. For example, if every stage produced a pulse shrinkage of 0.2 ns, then the 13 cascaded stages in a 64.times.1 input switch would cause a pulse shrinkage of 13.times.0.2=2.6 ns. Thus, an input pulse of 7 ns (corresponding to 150 Mb information rate) would shrink at the output to 4.4 ns. This would prevent one 64 module from driving the next without reclocking the output. and expanding the 4.4 ns pulses back to 7 ns. In FIG. 1, constant pulse width is difficult to achieve because, for example, a rising edge at input 3 will appear as a rising edge at gate 3. Since gate 3 is an inverter and not identical to gate 2, there cannot be exact compensation of rise and fall delay.